1. Field of the Invention
The present invention relates to random access memory (RAM) control, and more particularly, to a memory control circuit and a related method.
2. Description of the Prior Art
With the development of the information technology industries, semiconductor component technologies progress rapidly. In order to increase the writing or reading speed of synchronous dynamic random access memory (SDRAM), double data rate (DDR) technology is introduced for related applications, where SDRAM utilizing DDR technology can be referred to as DDR SDRAM.
The data accessing of conventional SDRAM corresponds to a specific edge of each of a plurality of periods of a clock signal. For example, the specific edge is a rising edge. As the data accessing of DDR SDRAM corresponds to the rising and falling edges of each of a plurality of periods of a clock signal, the data accessing speed of DDR SDRAM is twice as fast as the data accessing speed of conventional SDRAM if their clock signals have the same frequency.
A data strobe signal differing from a clock signal can be applied to DDR SDRAM for data accessing, where the data strobe signal mentioned above is also referred to as the DQS signal, and the signal format thereof is well known in the art. As shown in FIG. 1, when a write command WR is outputted, a plurality of periodic pulses should occur in the data strobe signal DQS after the data strobe signal DQS enters a low level. The rising and falling edges of these periodic pulses can be utilized as time references for writing data D0, D1, D2, D3, etc. carried by the data signal DQ into memory cells of a memory. In addition, within the waveform of the data strobe signal DQS shown in FIG. 1, the portion corresponding to the low level occurring before the periodic pulses appearance is referred to as the preamble. Additionally, the time interval between a rising edge of the clock signal VCLK around the time point when the write command WR is issued and the first rising edge of the data strobe signal DQS around the end of the preamble is defined as TDQSS.
When a memory circuit system operates at high frequencies, it is important to have the data strobe signal DQS that has a 50% duty cycle (as shown in FIG. 1). This provides the memory circuit system with approximately an equal amount of time on the high level phase and on the low level phase for transferring data into and out of the memory circuit system, such as latching rising edge data and latching falling edge data out of the memory circuit system. However, in some situations, a situation where the frequency of the clock signal VCLK is increased and the signal delay of some portions within the memory circuit system is not properly corrected, the data strobe signal DQS may not comply with a particular specification due to a duty cycle distortion. Once the periodic pulses of the data strobe signal DQS do not comply with a duty cycle defined by the specific specification mentioned above, the data carried by the data signal DQ cannot be guaranteed to be written into memory cells correctly.